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Semiconductor Products Sector
MMC2080/2075/D Rev. 0, 10/1999
MMC2080/2075
Advance Information
MMC2080/2075 Integrated Processor with Roaming FLEXTM Decoder
Part 1 Introduction
The MMC2080/2075 is designed to provide the messaging and paging marketplace with a powerful and flexible solution to carry communications design into the next millennium. The MMC2080 integrates two of Motorola's most successful product families, M*CORETM and the Roaming FLEXTM alphanumeric decoders, a combination that will set a new standard in the communications industry. Except for the FLEX decoder, the MMC2075 offers all features of the MMC2080. Both the The MMC2080/2075 are members of the low-power, high-performance M*CORE family of 32-bit microcontroller units (MCUs). The M*CORE is a streamlined execution engine that provides many of the performance enhancements found in mainstream reduced instruction set computers (RISCs). Combining performance, speed, and cost efficiency in a compact, low-power design, the M*CORE microRISC architecture is a natural solution for applications where battery life and systems cost are critical design goals. Given that a total system's components and processor core determine its power consumption, the instruction set architecture (ISA) for the M*CORE is designed to optimize the trade-off between performance and total power consumption. The result is system-wide reduction of total energy consumption with maintenance of acceptable performance levels. Memory power consumption (both on-chip and external) is a major factor in system energy consumption. By adopting 16-bit instruction encoding, and thus significantly decreasing the memory bandwidth needed for a high rate of instruction execution, the MMC2080/2075 minimizes the overhead of memory system energy consumption. The MMC2080/2075 also reduces power consumption by coupling a fully static design with dynamic power management and low-voltage operation. Versatile power management is achieved through automatic power downs of any internal functional blocks not needed on a clock-by-clock basis. Power conservation modes are also provided for absolute power conservation. A table of contents for this document appears on the following page. Figure 1 on page 3 and Figure 2 on page 4 provide simplified block diagrams of the MMC2080/2075.
This document contains information on a new product. Specifications and information herein are subject to change without notice. (c) Motorola, Inc., 1999. All rights reserved.
Part 1 1.1 1.2 1.3 1.4 1.5 1.6
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Conventions and Terminology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Integrated Roaming FLEX Protocol and the MMC2080 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Target Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Product Documentation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1 5 6 8 8 8 8
Part 2 Signal and Connection Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2.1 MMC2080/2075 Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2.2 Tables of Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Part 3 Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 3.1 General Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 3.2 Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Part 4 4.1 4.2 4.3 Pin-out and Package Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 BGA Details . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 PGA Details . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Ordering Drawings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Part 5 Design Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 5.1 Heat Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 5.2 Electrical Design Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
2
MMC2080/2075 Technical Data Preliminary
I/O JTAG POR DE TMS TCK TDI TDO TRST XTAL EXTAL MPD[7:0]/D[15:8] PLL SIM OnCE CPU SCI OSC (MPIO) INTC Timer1 CXFC RESET RSTOUT UCLK MPC7/URXD MPC6/UTXD MPC5/UCTS MPC4/URTS MPC3/TIC1 MPC2/TOC1 MPC1/TIC0 MPC0/TOC0 MPIO SPI1-FSC MPE4/LOCK MPE3/MOSI MPE2/MISO MPE1/SS MPE0/SCLK MPB[7:4]/ROW[3:0] MPB[3:0]/COL[3:0] MPA[5:0] CNFG FLEX Melody BGNT BREQ MLDY Arbiter SPI0 MMC2080 Only JTAG I/O
Timer0 96K ROM D[7:0] A[21:0] EB[1:0] BW8 WE OE TA ABORT BUSCLK IRQ SEL[2:0], SEL3 XBOOT Peripheral Bus
System Bus
6K RAM
External Bus Bridge
APB
Keypad
LOBAT EXTS[1:0] CLKOUT SYMCLK S[7:1] S0/IFIN
Figure 1. MMC2080/2075 144 Block Diagram (144-Pin Package)
Introduction Preliminary
3
I/O JTAG TC[2:0] DE TMS TCK TDI TDO TRST XTAL EXTAL MPD[7:0]/D[15:8] D[7:0] D[31:16] A[21:0] EB[1:0] DVLEB[1:0] BW8 WE OE TA TEA ABORT BUSCLK IRQ DSTAT[5:0] DVLMX SEL[2:0], SEL3 DVLSEL XBOOT DVL[1:0] SHS POR PLL SIM OnCE CPU SCI OSC (MPIO) INTC Timer1 CXFC RESET RSTOUT UCLK MPC7/URXD MPC6/UTXD MPC5/UCTS MPC4/URTS MPC3/TIC1 MPC2/TOC1 MPC1/TIC0 MPC0/TOC0 MPIO SPI1-FSC MPE4/LOCK MPE3/MOSI MPE2/MISO MPE1/SS MPE0/SCLK MPB[7:4]/ROW[3:0] MPB[3:0]/COL[3:0] MPA[5:0] CNFG FLEX Melody BGNT BREQ MLDY HIGHZ PULL_EN Arbiter SPI0 MMC2080 Only JTAG I/O
Timer0 96K ROM Peripheral Bus
System Bus
6K RAM
External Bus Bridge
APB
Keypad
LOBAT EXTS[1:0] CLKOUT SYMCLK S[7:1] S0/IFIN
Figure 2. MMC2080/2075 DVL Block Diagram (208-Pin Package)
4
MMC2080/2075 Technical Data Preliminary
Conventions and Terminology
1.1 Conventions and Terminology
This document uses the following conventions: * * * * * * * * OVERBAR is used to indicate a signal that is active when pulled low: for example, RESET. Logic level one is a voltage that corresponds to Boolean true (1) state. Logic level zero is a voltage that corresponds to Boolean false (0) state. To set a bit or bits means to establish logic level one. To clear a bit or bits means to establish logic level zero. A signal is an electronic construct whose state or changes in state convey information. A pin is an external physical connection. The same pin can be used to connect a number of signals. Asserted means that a discrete signal is in active logic state. -- Active low signals change from logic level one to logic level zero. -- Active high signals change from logic level zero to logic level one. * Deasserted means that an asserted discrete signal changes logic state. -- Active low signals change from logic level zero to logic level one. -- Active high signals change from logic level on to logic level zero. * LSB means least significant bit or bits. MSB means most significant bit or bits. References to low and high bytes or words are spelled out.
Please refer to the examples in Table 1.
Table 1. Data Conventions
Signal/Symbol PIN PIN PIN PIN Logic State True False True False Signal State Asserted Deasserted Asserted Deasserted Voltage VIL/VOL VIH/VOH VIH/VOH VIL/VOL
Introduction Preliminary
5
Features
1.2 Features
The MMC2080/2075 offers the following suite of features. * M*CORETM RISC Processor -- 32-bit load/store M*CORE RISC architecture -- Fixed 16-bit instruction length -- 16-entry 32-bit general-purpose register file -- 32-bit internal address and data buses -- Efficient, four-stage, fully interlocked execution pipeline -- Single-cycle execution for most instructions; two cycles for branches and memory accesses -- Special branch, byte, and bit manipulation instructions -- Support for byte, halfword, and word memory accesses -- Fast interrupt support via vectoring/auto-vectoring and a 16-entry dedicated alternate register file * Integrated Roaming FLEX alphanumeric decoder (MMC2080 only) -- FLEX paging protocol signal processor -- 1600, 3200, and 6400 bits per second (bps) decoding -- Highly programmable receiver control -- FLEX message fragmentation and group messaging support -- SSID and NID roaming support -- Internal demodulator and data slicer -- Improved battery savings via partial address correlation and intermittent receiver clock -- Full support for revision G1.9 of the FLEX protocol -- External CAP code access through parallel or serial FLASH/PROM * On-chip memory -- 24 K x 32 CPU ROM (96 K) -- 1.5 K x 32 CPU RAM (6 K) * On-chip peripherals -- Asynchronous serial communications interface (SCI) with IrDA capability -- Synchronous serial peripheral interface (SPI) -- Frequency synthesizer controller (FSC) -- Melody generator -- 4 x 4 keypad interface -- Multipurpose I/O ports (MPIO) -- Two 16-bit general purpose timers -- Time-of-day (TOD) timer -- Watchdog timer -- Vectored interrupt controller with 16 programmable priority levels
6
MMC2080/2075 Technical Data Preliminary
Features
-- Oscillator and PLL with software selectable speeds -- AMBA peripheral bridge depipelines system bus for simpler peripheral bus -- 8/16-bit external system bus with 22-bit address bus * Operating features -- Processor operation to 10 MHz over full operating range -- Low-power modes -- OnCETM (On-Chip Emulation) debug module -- Voltage range 1.8 V to 3.6 V; temperature range -20 C to 85 C -- Chip-select outputs for four external devices (4 Mbyte per chip select, 16 Mbyte directly addressable) -- Programmable wait states for external accesses -- External boot option -- External bus interface that accepts internal, half-word, and byte transfers -- External device that may become system bus master * Development tools -- Development option (different package) that adds select to bypass internal ROM -- Development option (different package) that extends external bus to 32 bits -- External bus that can display internal transfers
Introduction Preliminary
7
Integrated Roaming FLEX Protocol and the MMC2080
1.3 Integrated Roaming FLEX Protocol and the MMC2080
The MMC2080 integrates several field-proven technologies, providing a versatile Roaming FLEX solution. The MMC2080 operates the integrated FLEX decoder in an efficient power-consumption mode, allowing the CPU to operate in a low-power mode when monitoring for message information. The Roaming FLEX protocol is a multichannel, high-performance protocol that leading service providers worldwide have adopted as a de facto standard for roaming paging. Roaming FLEX protocol gives service providers increased capacity, added reliability, enhanced pager battery performance, and the ability to control a PLLsynthesized receiver and to receive paging messages from a list of paging channels. Finally, the MMC2080 gives the service provider an upward migration path that is completely transparent to the end user.
1.4 Target Applications
The MMC2080/2075 is intended for use in wireless and paging applications. The MMC2080 is designed for applications needing an M*CORE CPU coupled with a roaming FLEX Decoder. The MMC2075 is intended for applications requiring the processing power and flexibility of the M*CORE CPU.
1.5 Product Documentation
The three documents listed in Table 2 are required for a complete description of the MMC2080/2075 and are necessary to design properly with the part. Documentation is available from a local Motorola distributor, a Motorola Semiconductor Products Sector sales office, a Motorola Literature Distribution Center, or the World Wide Web. See the last page of this document for contact information.
Table 2. MMC2080/2075 Documentation
Document Name M*CORE Reference Manual Description of Contents Detailed description of the M*CORE MCU and instruction set Detailed description of the MMC2080/2075 memory, peripherals, and interfaces MMC2080/2075 pin and package descriptions; electrical and timing specifications Order Number MCORERM/AD
MMC2080/2075 User's Manual
MMC2080/2075UM/D
MMC2080/2075 Technical Data
MMC2080/2075/D
1.6 Ordering Information
Table 3 lists the information you need to supply when placing an order. Consult a Motorola Semiconductor Products Sector sales office or authorized distributor to determine availability and to order parts.
Table 3. MMC2080/2075 Ordering Information
Part MMC2080 MMC2075 MMC2080 MMC2075 Supply Voltage 3V 3V 3V 3V Package Type 12 mm x 12 mm MAP BGA 12 mm x 12 mm MAP BGA 43 mm x 43 mm Ceramic PGA 43 mm x 43 mm Ceramic PGA Pin Count 144 144 208 208 Order Number MMC2080VF001 MMC2075VF001 Contact Factory Development Use Only
8
MMC2080/2075 Technical Data Preliminary
MMC2080/2075 Pin Descriptions
Part 2 Signal and Connection Descriptions
The pins and signals of the MMC2080/2075 are described in the following sections. Figure 3 on page 10 and Figure 4 on page 11 are top and bottom views, respectively, of the 12 mm x 12 mm MAP Ball Grid Array (BGA) package, and Figure 5 on page 12 and Figure 6 on page 13 are top and bottom views, respectively, of the 43 mm x 43 mm ceramic Pin Grid Array (PGA) package, showing the pin-outs. Table 4 on page 14 and Table 5 on page 17 list the pins by number and signal name. Figure 7 on page 21 is a representational pin-out of the chip, grouping the signals by their function. Table 6 on page 20 identifies the number of signals for each group and refers to Table 8 on page 23 through Table 20 on page 27, which are organized according to signal type and give a brief description of each signal pin.
2.1 MMC2080/2075 Pin Descriptions
The following section provides information about the available packages for this product, including diagrams of the package pin-outs and tables describing how the signals of the MMC2080/2075 are allocated. There are two packages for each part: * * The 144-pin I/O, STD small ball (SMBALL) mold array process (MAP) ball grid array (BGA), 12 mm x 12 mm package. Table 4 on page 14 identifies the signal associated with each pin. The 208-pin I/O, PGA, 43 mm x 43 mm ceramic package. Table 5 on page 17 identifies the signal associated with each pin.
Signal and Connection Descriptions Preliminary
9
MMC2080/2075 Pin Descriptions
1
2
3
4
5
6
7
8
9
10
11
12
13
A B C D E F G H J K L M N
VSS I/O MPB7/ ROW3 IRQ VDD Core
MPB5/ ROW1 MPB6/ ROW2 MPA0
EB1
MPB2/ COL2 ABORT MPB3/ COL3 VSS Core
MPB0/ COL0 EB0 MPB1/ COL1 OE
VDD I/O VDD Core TA
SEL1
VSS I/O S7*
VSS Core S4*
S2*
LOBAT* CLKOUT* VSS I/O EXTS0* MPE4/ LOCK EXTAL
VDD I/O EXTS1* VSS I/O MPE3/ MOSI VSS OSC A21 VSS Core BREQ
BW8 MPB4/ ROW0 MPA1
SEL0
S1*
MLDY VDD I/O VDD Core
SEL2
S6*
S3*
SYMCLK
D0
WE
SEL3
S5*
XBOOT
S0/IFIN
BUSCLK VDD I/O MPA5 VSS I/O VSS Core D11
VSS I/O MPA3
D2
D1 VDD I/O D4 VDD I/O BGNT MPC0/ TOC0 MPC3/ TIC1 MPC2/ TOC1 VSS I/O MPC5/ UCTS A5 VDD Core MPC6/ UTXD MPC7/ URXD MPC4/ URTS
VDD OSC VDD PLL A20
XTAL VSS PLL A18 VDD I/O VSS I/O A13 VDD I/O VDD I/O RESET
MPA2
CXFC
MPA4
D3
A19
D8
D9
A16 MPE1/ SS A1 VSS Core A2 MPC1/ TIC0 A8 VDD I/O A7 A12
A17 MPE2/ MISO MPE0/ SCLK VSS I/O RSTOUT
D5
D10 VDD Core D13 VSS I/O TMS
A15
D12
TDI
A14
D6
D7
TDO
A10
A11
D14 VDD I/O
D15
TRST
A3
TEST
UCLK VSS I/O
TCK
A0
A4
A6
A9
DE
Top View
* Signal available only in 2080
Figure 3. MMC2080/2075 BGA (144-Pin) Top View
10
MMC2080/2075 Technical Data Preliminary
MMC2080/2075 Pin Descriptions
13
12
11
10
9
8
7
6
5
4
3
2
1
VDD I/O EXTS1* VSS I/O MPE3/ MOSI VSS OSC A21 VSS Core BREQ
CLKOUT*
LOBAT* VSS I/O EXTS0* MPE4/ LOCK EXTAL
S2 *
VSS Core S4*
VSS I/O S7*
SEL1
VDD I/O VDD Core TA
MPB0/ COL0 EB0 MPB1/ COL1 OE
MPB2/ COL2 ABORT MPB3/ COL3 VSS Core
EB1
MPB5/ ROW1 MPB6/ ROW2 MPA0
VSS I/O MPB7/ ROW3 IRQ VDD Core
A B C D E F G H J K L M N
MLDY VDD I/O VDD Core
S1*
SEL0
BW8 MPB4/ ROW0 MPA1
SYMCLK
S3*
S6*
SEL2
S0/IFIN
XBOOT
S5*
SEL3
WE
D0
XTAL VSS PLL A18 VDD I/O VSS I/O A13 VDD I/O VDD I/O RESET
VDD OSC VDD PLL A20
D1 VDD I/O D4 VDD I/O BGNT VDD Core MPC6/ UTXD MPC7/ URXD MPC4/ URTS MPC5/ UCTS A5 MPC0/ TOC0 MPC3/ TIC1 MPC2/ TOC1 VSS I/O
D2
VSS I/O MPA3
BUSCLK VDD I/O MPA5 VSS I/O VSS Core D11
CXFC
MPA2
A19
D3
MPA4
A17 MPE2/ MISO MPE0/ SCLK VSS I/O RSTOUT
A16 MPE1/ SS A12 A8 VDD I/O A7 A1 VSS Core A2 MPC1/ TIC0
D9
D8
A15
D10 VDD Core D13 VSS I/O TMS
D5
A14
TDI
D12
A11
A10
TDO
D7
D6
UCLK VSS I/O
TEST
A3
TRST
D15
D14 VDD I/O
DE
A9
A6
A4
A0
TCK
Bottom View
* Signal available only in 2080
Figure 4. MMC2080/2075 BGA (144-Pin) Bottom View
Signal and Connection Descriptions Preliminary
11
MMC2080/2075 Pin Descriptions
1 A B C D E F G H J K L M N P R T U
MPB6/ ROW2 NC
2
MPB4/ ROW0 NC
3
BW8
4
MPB2/ COL2
5
MPB0/ COL0
6
TA MPB1/ COL1 ABORT
7
DVLEB1
8
SEL3
9
SEL1
10
VSS I/O S5*
11
DVLEB0
12
VSS Core S3*
13
S2 *
14
15
16
NC
17
MLDY
S0/IFIN DVLMX
MPB5/ PULL_EN MPB3/ COL3 ROW1 NC VSS I/O MPA0 NC D16
WE
SEL2 VDD I/O VDD Core
S7*
S6*
DVL1 VSS I/O
LOBAT* VDD I/O NC
NC
NC
EXTS0*
IRQ VDD Core BUSCLK
NC
EB0
TEA
XBOOT
S1*
DVL0
NC
EXTS1* DSTAT4
MPA1
NC MPB7/ ROW3 VSS Core D1
NC
EB1
OE
SEL0
S4*
SYMCLK DVLSEL CLKOUT*
NC VDD I/O
DSTAT5 DSTAT1 VSS I/O MPE3/ MOSI VDD OSC XTAL VDD PLL VSS PLL TC1
D2
NC
D17
MPA2 VDD I/O D18
D0 VSS I/O VDD I/O D20
DSTAT3 DSTAT2 DSTAT0 MPE4/ LOCK EXTAL VDD Core VSS OSC A20
MPA4
TC2
MPA5
MPA3
CXFC VSS Core BREQ
D4
D19 VSS I/O VSS Core D23
D3
A21
D8 VDD I/O D22
D9
D21
A17
A15 MPE2/ MISO MPE0/ SCLK VDD I/O VSS I/O NC
D10
BGNT
A14
A18
A19 VDD I/O VSS I/O A13
D12
D25
A11
A16 MPE1/ SS A12
D5
D24
D6
NC VSS Core A0 MPC6/ UTXD MPC4/ URTS A5 MPC5/ UCTS
UCLK
D11 VDD Core D13
D7
NC
NC VDD I/O TMS
TCK VSS I/O TDO
TC0
D26
A3 MPC2/ TOC1 MPC0/ TOC0 A4
A8
DE
NC
NC
D14
NC
HIGHZ
D27 MPC1/ TIC0 MPC3/ TIC1
A7 VDD Core MPC7/ URXD
TEST VDD I/O D29
RSTOUT
NC
NC
NC
NC
NC
A1
D28 VSS I/O
A10
D31
RESET
SHS VSS I/O
NC
D15
NC
NC
TDI
TRST
A2
A6
A9
D30
NC
Top View
* Signal available only in 2080
Figure 5. MMC2080/2075 PGA (208-Pin) Top View
12
MMC2080/2075 Technical Data Preliminary
MMC2080/2075 Pin Descriptions
17
MLDY
16
NC
15
14
13
S2 *
12
VSS Core S3*
11
DVLEB0
10
VSS I/O S5*
9
SEL1
8
SEL3
7
DVLEB1
6
TA MPB1/ COL1 ABORT
5
MPB0/ COL0
4
MPB2/ COL2
3
BW8
2
MPB4/ ROW0 NC
1
MPB6/ ROW2 NC
DVLMX S0/IFIN
A B C D E F G H J K L M N P R T U
EXTS0*
NC
NC
LOBAT* VDD I/O NC
DVL1 VSS I/O
S6*
S7*
SEL2 VDD I/O VDD Core
WE
MPB3/ PULL_EN MPB5/ COL3 ROW1 D16 NC NC VSS I/O MPA0
DSTAT4 EXTS1*
NC
DVL0
S1*
XBOOT
TEA
EB0
NC
IRQ VDD Core BUSCLK
DSTAT1 DSTAT5 MPE3/ MOSI VDD OSC XTAL VDD PLL VSS PLL TC1 VSS I/O
NC VDD I/O
CLKOUT DVLSEL SYMCLK * *
S4*
SEL0
OE
EB1
NC
NC MPB7/ ROW3 VSS Core D1
MPA1
NC
D2
DSTAT0 DSTAT2 DSTAT3 VDD Core VSS OSC A20 MPE4/ LOCK EXTAL
D0 VSS I/O VDD I/O D20
MPA2 VDD I/O D18
D17
TC2
MPA4
CXFC VSS Core BREQ
MPA3
MPA5
A21
D3
D19 VSS I/O VSS Core D23
D4
A15 MPE2/ MISO MPE0/ SCLK VDD I/O VSS I/O NC
A17
D21
D9
D8 VDD I/O D22
A19 VDD I/O VSS I/O A13
A18
A14
BGNT
D10
A16 MPE1/ SS A12
A11
D25
D12
UCLK MPC6/ UTXD MPC4/ URTS A5 MPC5/ UCTS VSS Core A0
NC
D6
D24
D5
NC
NC
DE
A8
A3 MPC2/ TOC1 MPC0/ TOC0 A4
D26
TC0
TCK VSS I/O TDO
NC VDD I/O TMS
NC
D7
D11 VDD Core D13
NC
NC
NC
RSTOUT
TEST VDD I/O D29
A7 VDD Core MPC7/ URXD
D27 MPC1/ TIC0 MPC3/ TIC1
HIGHZ
NC
D14
NC
SHS VSS I/O
RESET
D31
A10
D28 VSS I/O
A1
NC
NC
NC
D30
A9
A6
A2
TRST
TDI
NC
NC
D15
Bottom View
* Signal available only in 2080
Figure 6. MMC2080/2075 PGA (208-Pin) Bottom View
Signal and Connection Descriptions Preliminary
13
MMC2080/2075 Pin Descriptions
Table 4. MMC2080/2075 BGA (144-Pin) Signal ID by Pin Number (Sheet 1 of 3)
Pin Number A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 B13 C1 C2 Vss I/O MPB5/ROW1 BW8 MPB2/COL2 MPB0/COL0 Vdd I/O SEL1 Vss I/O Vss Core S2 (2080 Only) LOBAT (2080 Only) CLKOUT (2080 Only) Vdd I/O MPB7/ROW3 MPB6/ROW2 BW8 ABORT EB0 Vdd Core SEL0 S7 (2080 Only) S4 (2080 Only) S1 (2080 Only) Vss I/O MLDY EXTS1 (2080 Only) IRQ MPA0 Signal Name Pin Number G10 G11 G12 G13 H1 H2 H3 H4 H10 H11 H12 H13 J1 J2 J3 J4 J10 J11 J12 J13 K1 K2 K3 K4 K5 K6 K7 K8 Signal Name A20 A19 A18 Vss Core Vss I/O D8 D9 Vdd I/O A16 A17 Vdd I/O BREQ Vss Core D5 D10 BGNT MPE1/SS MPE2/MIS0 Vss I/O A15 D11 D12 Vdd Core TDI A1 MPC0/TOC0 MPC5/UCTS Vdd Core
14
MMC2080/2075 Technical Data Preliminary
MMC2080/2075 Pin Descriptions
Table 4. MMC2080/2075 BGA (144-Pin) Signal ID by Pin Number (Sheet 2 of 3)
Pin Number C3 C4 C5 C6 C7 C8 C9 C10 C11 C12 C13 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 E1 E2 E3 E4 Signal Name MPB4/ROW0 MPB3/COL3 MPB1/COL1 TA SEL2 S6 (2080 Only) S3 (2080 Only) SYMCLK (2080 Only) EXTS0 (2080 Only) Vdd I/O Vss I/O Vdd Core D0 MPA1 Vss CORE OE WE SEL3 S5 (2080 Only) XBOOT S0/IFIN (2080 only) MPE4/LOCK Vdd Core MPE3/MOSI BUSCLK Vss I/O D2 D1 Pin Number K9 K10 K11 K12 K13 L1 L2 L3 L4 L5 L6 L7 L8 L9 L10 L11 L12 L13 M1 M2 M3 M4 M5 M6 M7 M8 M9 M10 Signal Name A8 A12 MPE0/SCLK A13 A14 D6 D7 D13 TDO Vss Core MPC3/TIC1 A5 MPC6/UTXD Vdd I/O A10 Vss I/O Vdd I/O A11 D14 D15 Vss I/O TRST A2 MPC2/TOC1 A3 MPC7/URXD A7 TEST
Signal and Connection Descriptions Preliminary
15
MMC2080/2075 Pin Descriptions
Table 4. MMC2080/2075 BGA (144-Pin) Signal ID by Pin Number (Sheet 3 of 3)
Pin Number E10 E11 E12 E13 F1 F2 F3 F4 F10 F11 F12 F13 G1 G2 G3 G4 Signal Name Vdd OSC EXTAL XTAL Vss OSC Vdd I/O MPA3 MPA2 Vdd I/O Vdd PLL CXFC Vss PLL A21 MPA5 MPA4 D3 D4 Pin Number M11 M12 M13 N1 N2 N3 N4 N5 N6 N7 N8 N9 N10 N11 N12 N13 Signal Name RSTOUT Vdd I/O UCLK Vdd I/O TCK TMS A0 MPC1/TIC0 Vss I/O A4 MPC4/URTS A6 A9 DE RESET Vss I/O
16
MMC2080/2075 Technical Data Preliminary
MMC2080/2075 Pin Descriptions
Table 5. MMC2080/2075 PGA (208-Pin) Signal ID by Pin Number (Sheet 1 of 4)
Pin Number A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A17 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 B13 B14 Signal Name MPB6/ROW2 MPB4/ROW0 BW8 MPB2/COL2 MPB0/COL0 TA DVLEB1 SEL3 SEL1 Vss I/O DVLEB0 Vss Core S2 (2080 Only) S0/IFIN (2080 only) DVLMX MLDY MPB5/ROW1 PULL_EN MPB3/COL3 MPB1/COL1 WE SEL2 S7 (2080 Only) S5 (2080 Only) S6 (2080 Only) S3 (2080 Only) DVL1 LOBAT (2080 Only) Pin Number J4 J14 J15 J16 J17 K1 K2 K3 K4 K14 K15 K16 K17 L1 L2 L3 L4 L14 L15 L16 L17 M1 M2 M3 M4 M14 M15 M16 Signal Name D3 A21 A20 Vss Core Vss PLL D8 Vss I/O D9 D21 A17 A15 BREQ TC1 Vdd I/O Vss Core D10 BGNT A14 MPE2/MIS0 A18 A19 D22 D23 D12 D25 A11 MPE0/SCLK A16
Signal and Connection Descriptions Preliminary
17
MMC2080/2075 Pin Descriptions
Table 5. MMC2080/2075 PGA (208-Pin) Signal ID by Pin Number (Sheet 2 of 4)
Pin Number B17 C1 C5 C6 C7 C8 C9 C10 C11 C12 C13 C14 C16 C17 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D16 Signal Name EXTS0 (2080 Only) IRQ D16 ABORT EB0 Vdd I/O TEA XBOOT S1 (2080 Only) DVLO Vss I/O Vdd I/O EXTS1 (2080 Only) DSTAT4 Vdd Core MPA1 Vss I/O EB1 OE Vdd Core OE VddCORE SEL0 S4 (2080 Only) SYMCLK (2080 Only) DVLSEL CLKOUT (2080 Only) DSTAT5 Pin Number M17 N1 N2 N3 N14 N15 N16 N17 P1 P2 P3 P4 P5 P6 P7 P8 P9 P10 P11 P12 P15 P16 P17 R1 R2 R4 R5 R6 Signal Name Vdd I/O D5 D24 D6 UCLK Vdd I/O MPE1/SS Vss I/O D11 D7 TCK TC0 TCK TC0 D26 VssCore A3 MPC6/UTXD A8 DE Vss I/O A12 A13 Vdd Core D14 Vdd I/O Vss I/O HIGHZ
18
MMC2080/2075 Technical Data Preliminary
MMC2080/2075 Pin Descriptions
Table 5. MMC2080/2075 PGA (208-Pin) Signal ID by Pin Number (Sheet 3 of 4)
Pin Number D17 E1 E2 E3 E4 E15 E16 E17 F1 F2 F3 F4 F14 F15 F16 F17 G1 G2 G3 G4 G14 G15 G16 G17 H1 H2 H3 H4 Signal Name DSTAT1 BUSCLK D2 MPA0 MPB7/ROW3 Vdd I/O Vss I/O MPE3/MOSI D17 MPA2 D0 Vss CORE DSTAT3 DSTAT2 DSTAT0 Vdd OSC MPA4 Vdd I/O Vss I/O D1 MPE4/LOCK Vdd Core TC2 XTAL MPA5 D18 Vdd I/O MPA3 Pin Number R7 R8 R9 R10 R11 R12 R13 T1 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 U1 U4 U5 U6 U7 U8 U9 Signal Name D27 A0 MPC2/TOC1 MPC4/URTS A7 TEST RSTOUT D13 TMS TDO A1 MPC1/TIC0 D28 MPC0/TOC0 A5 Vdd Core Vdd I/O A10 D31 RESET SHS D15 TDI TRST A2 MPC3/TIC1 Vss I/O A4
Signal and Connection Descriptions Preliminary
19
Tables of Signals
Table 5. MMC2080/2075 PGA (208-Pin) Signal ID by Pin Number (Sheet 4 of 4)
Pin Number H14 H15 H16 H17 J1 J2 J3 EXTAL Vss OSC CXFC Vdd PLL D4 D19 D20 Signal Name Pin Number U10 U11 U12 U13 U14 U15 U16 Signal Name MPC5/UCTS MPC7/URXD D29 A6 A9 D30 Vss I/O
2.2 Tables of Signals
The MMC2080 input and output signals are organized into functional groups in Table 6 and in Figure 7 on page 21. Table 7 on page 22 displays data relating to I/O cell names, including descriptions and the availability of Hi-Z impedance, pull-up resistors, and high drive-current capability. Table 8 on page 23 through Table 20 on page 27 are organized according to signal type and give a brief description of each signal pin. Package type is indicated as "N" for the 144-pin normal-function package. All pins are available in the 208-pin development extensions package.
Table 6. MMC2080 Signal Functional Group Organization
Functional Group Arbitration signals External system bus signals Development extensions (208-pin package only) FLEX signals FSC/SPI signals SCI signals Timer signals Melody generator signals Keypad signals Dedicated MPIO signals SIM signals JTAG/OnCE signals Clock and power Number of Signals 2 52 34 13 5 5 4 1 8 6 2 6 40 Detailed Description Table 20 on page 27 Table 8 on page 23 Table 9 on page 24 Table 10 on page 25 Table 11 on page 25 Table 12 on page 25 Table 13 on page 26 Table 14 on page 26 Table 15 on page 26 Table 16 on page 26 Table 17 on page 26 Table 18 on page 27 Table 19 on page 27
20
MMC2080/2075 Technical Data Preliminary
Tables of Signals
MMC2080
Arbitration Signals BREQ BGNT Arbitration Request Arbitration Grant Receive Data Transmit Data Clear-To-Send Request-To-Send UART Clock Timer1 Input Capture Timer1 Output Capture Timer0 Input Capture Timer0 Output Capture Generator Waveform Row Detect Column Detect MPC7/URXD MPC6/UTXD MPC5/UCTS MPC4/URTS UCLK MPC3/TIC1 MPC2/TOC1 MPC1/TIC0 MPC0/TOC0 MLDY MPB[7:4]/ROW[3:0] MPB[3:0]/COL[3:0] MPA[5:0]
SCI Signals
External System Bus Signals
MPD[7:0]/D[15:8] D[7:0] A[21:0] EB0-1 BW8 WE OE TA ABORT BUSCLK SEL0-3 XBOOT IRQ
High-Order Data Bus Low-Order Data Bus Address Byte Enable Bus Width (8-Bit) Data Direction Output Enable Transfer Acknowledge Data Transfer Abort External Bus Clock External Device Select External Boot Interrupt Request
Timer Signals Melody Generator Signal Keypad Signals MPIO Signals SIM Signals
Development Extensions (208-Pin Package)
D[31:16] DVLEB0-1 DVL0-1 DVLSEL DSTAT0-5 DVLMX TC0-2 TEA HIGHZ PULL_EN SHS LOBAT EXTS0-1 CLKOUT SYMCLK S1-7 S0/IFIN
Extension Byte Enable Development Mode Development Select Development Status Status Output Select Transfer Code Transfer Error Acknowledge Tri-State Disable Pull-up Enable Show Cycle Strobe Low Battery Extension Symbol Clock Output Symbol Clock Serial Port Serial Port
Master Reset Reset Output Test Mode Select Test Clock Test Data In Test Data Out TAP Reset Debug Enable Oscillator Circuit Input Oscillator Circuit Output PLL Filter Capacitor Core Power Core Ground I/O Pad Power I/O Pad Ground
VDD RESET RSTOUT TMS TCK TDI TDO TRST DE EXTAL XTAL CXFC VDDCORE[5] VSSCORE[5] IOVDD[11] IOVSS[11]
JTAG/OnCE Signals
FLEX Signals
Clock and Power
FSC/SPI Signals
MPE4/LOCK MPE3/MOSI MPE2/MISO MPE1/SS MPE0/SCLK
Synthesizer Lock Master in/Slave Out Master Out/Slave In Slave Select Serial Clock
Oscillator Power Oscillator Ground PLL Power PLL Ground
OSCVDD OSCVSS PLLVDD PLLVSS
Figure 7. MMC2080 Signal Group Organization
Signal and Connection Descriptions Preliminary
21
Tables of Signals
Table 7. I/O Cell Description
I/O Cell Name Description Hi-Z Pull-up High Drive Capable Y
OTP
Tri-state output with selectable drive strength; always enabled with strong drive except during JTAG Hi-Z command or unless otherwise stated Input with hysteresis INHP with selectable pull-up enable INHP and OTP INHPP and OTP High-current IOHPPH Analog input/output (same cell)
Y
N
INHP INHPP IOHP IOHPPH SWIOP AIN/AOT
N N Y Y Y N
N Y N Y Y N
N N Y Y Y N
22
MMC2080/2075 Technical Data Preliminary
Tables of Signals
Table 8. External System Bus Signals
Signal Name MPD[7:0]/D[15:8] Dir I/O N Y I/O Cell IOHPPH Description High-Order Data Bus--May be used as general I/O when the data bus is configured as an 8-bit bus. Output drivers are disabled and pull-up resistors are enabled during reset. Low-Order Data Bus--Output drivers are disabled and pull-up resistors are enabled during reset. Address--Input when BGNT is low; otherwise output. Twentytwo bits is a 4 Mbyte address space. Byte Enable (active low)--Input when BGNT is low; otherwise output. EB0 enables D[15:8] and EB1 enables D[7:0]. When the data bus is configured as an 8-bit bus, EB0 is always released (high) and EB1 is always asserted (low). Bus Width 8 (open-drain, active low)--If this pin is driven low either externally or internally, the external bus functions as an 8bit bus. Write Enable (active low)--Input when BGNT is low. When WE is low, data is driven by an external device and received by the MMC2080. Output when BGNT is high. When WE is low, data is driven by the MMC2080 and received by an external device. Output Enable (active low)--Input when BGNT is low; when OE is high, D[7:0] (and D[15:8] when in 16-bit mode) external data drivers are disabled. Output when BGNT is high; when OE is high, drivers are disabled. Transfer Acknowledge (active low)--An external transaction continues when this pin is high. When low, the external data transfer cycle will complete. When MONITOR mode is set. TA also indicates the end of internal transactions. Data Transfer Abort (active low)--When a transaction is aborted, this pin is driven low. External Bus Clock. External Device Select--SEL0 is always active low; SEL[3:1] may be individually programmed as active low or active high. After reset, SEL3 is active high. SEL1 and SEL2 are active low after restart. External Boot (active low)--If this pin is low after a reset, the external boot portion of the system memory map is enabled; otherwise the internal boot map is enabled. Interrupt Request--This is driven high when either a normal interrupt or a fast interrupt is generated by the interrupt controller.
D[7:0]
I/O
Y
IOHPPH
A[21:0]
I/O
Y
IOHP
EB[1:0]
I/O
Y
IOHP
BW8
I/O
Y
IOHPPH
WE
I/O
Y
IOHP
OE
I/O
Y
IOHP
TA
O
Y
OTP
ABORT
O
Y
OTP
BUSCLK SEL[3:0]
O O
Y Y
OTP OTP
XBOOT
I
Y
INHPP
IRQ
O
Y
OTP
Signal and Connection Descriptions Preliminary
23
Tables of Signals
Table 9. Development Extensions (208-Pin Package)
Signal Name D[31:16] Dir I/O N N I/O Cell IOHPPH Description Extension to provide a 32-bit external bus. The bus is enabled when either DVL0 or _DVL0 is asserted. Byte Enable (active low)--Input when BGNT is low; otherwise output. DVLEB0 enables D[31:24] and DVLEB1 enables D[23:16]. Development Mode--When DVL1 is low, the internal ROM is bypassed. If the ROM space is addressed when DVL1 is low and XBOOT is high, the 32-bit extension is enabled and DVLSEL is asserted to select an external memory. When DVL0 is low, the 32-bit bus extension is enabled for external bus masters (BGNT is low) and for debug monitor modes. DVLSEL O N OTP Development Select (active low)--When DVL1 is low and XBOOT is high, this output is asserted when the internal ROM locations are addressed. Selects the output of DSTAT[5:0]. When DVLMX is high, DSTAT is the low-order 6 bits of the interrupt vector. When DVLMX is low, DSTAT[3:0] is the M*CORE pipeline status, PSTAT[3:0], and DSTAT[5:4] is the transfer size in M*CORE format. Processor Transfer Code. Transfer Error Acknowledge (active low). Tri-State Disable (active low)--When asserted (low), all tri-state outputs are disabled (high-z). This performs the same function as the JTAG HIGHZ command. Enable Pull-up Resistors--When low, all pull-up resistors (except the pull-up resistor on this I/O cell) are disabled. Show Cycle Strobe (active low)-- Strobes low when data is valid.
DVLEB[1:0]
I/O
N
IOHPPH
DVL[1:0]
I
N
INHPP
DVLMX DSTAT[5:0]
I O
N N
INHPP OTP
TC[2:0] TEA HIGHZ
O I I
N N N
OTP INHPP INHPP
PULL_EN
I
N
INHPP
SHS
O
N
OTP
24
MMC2080/2075 Technical Data Preliminary
Tables of Signals
Table 10. FLEX Signals (MMC2080 Only)
Signal Name LOBAT Dir In N Y I/O Cell INHP Description Low Battery--LOBAT is an input signal to indicate to the MMC2080 when external battery power is going low. (An external voltage sensing circuit is required.) Polarity is programmable. External Symbol --EXTS 1 is the MSB of the current FLEX symbol. EXTS0 is the LSB of the current FLEX symbol. These pins are used when demodulation is being performed externally. Clock Output--CLKOUT is programmable as a 38.4 or 40 kHz clock output (derived from oscillator). Recovered Symbol Clock--Data is synchronized to the internal clock, and this recovered clock output enhances lock-on capability by reducing jitter from cable-induced noise. Control Lines 1-7--These signals are the seven additional receiver control lines. Selectable polarity. S0--This signal is a receiver control output line when the IDE bit is clear (that is, the internal demodulator is disabled). IFIN--This signal is a limited IF input when the IDE bit is set (that is, the internal demodulator is enabled).
EXTS[1:0]
In
Y
IOHP
CLKOUT*
O
Y
OTP
SYMCLK
O
Y
OTP
S[7:1]
O
Y
OTP
S0/IFIN
I/O
Y
IOHP
Table 11. FSC/SPI1 Signals
Signal Name MPE4/LOCK MPE3/MOSI MPE2/MISO MPE1/SS MPE0/SCLK Dir I/O I/O I/O I/O I/O N Y Y Y Y Y I/O Cell IOHPPH IOHPPH IOHPPH IOHPPH IOHPPH Description External Synthesizer Lock Input--PIO when SPI1 is disabled Master-out / Slave-in--PIO when SPI1 is disabled Master-in / Slave-out--PIO when SPI1 is disabled Slave Select (selectable polarity)--PIO when SPI1 is disabled Serial Clock--PIO when SPI1 is disabled
Table 12. SCI Signals
Signal Name MPC7/URXD MPC6/UTXD MPC5/UCTS Dir I/O I/O I/O N Y Y Y I/O Cell IOHPPH IOHPPH IOHPPH Description Receive Data--An input when used as URXD; otherwise a PIO Transmit Data--An output when used as UTXD; otherwise a PIO Clear-to-Send (active low)--An input when used as UCTS; otherwise a PIO Request-to-Send (active low)--An output when used as URTS; otherwise a PIO UART Clock
MPC4/URTS
I/O
Y
IOHPPH
UCLK
I/O
Y
IOHPPH
Signal and Connection Descriptions Preliminary
25
Tables of Signals
Table 13. Timer Signals
Signal Name MPC3/TIC1 Dir I/O N Y I/O Cell IOHPPH Description Timer1 Input Capture--An input when used as TIC1; otherwise a PIO Timer1 Output Capture--An output when used as TOC1; otherwise a PIO Timer0 Input Capture--An input when used as TIC0; otherwise a PIO Timer0 Output Capture--An output when used as TOC0; otherwise a PIO
MPC2/TOC1
I/O
Y
IOHPPH
MPC1/TIC0
I/O
Y
IOHPPH
MPC0/TOC0
I/O
Y
IOHPPH
Table 14. Melody Generator Signal
Signal Name MLDY Dir O N Y I/O Cell OTP Description Melody Generator Waveform
Table 15. Keypad Signals
Signal Name MPB[7:4]/ ROW[3:0] MPB[3:0]/ COL[3:0] Dir I/O N Y I/O Cell IOHPPH Description Row Detect--Inputs when used as row detect; otherwise a PIO
I/O
Y
IOHPPH
Column Select--Open-drain outputs when used as column select; otherwise a PIO
Table 16. MPIO Signals
Signal Name MPA[5:0] Dir I/O N Y I/O Cell SWIOP Description These bits can be individually programmed as input (with selectable pull-up resistor), output (with selectable drive strength), or external interrupt (with selectable assertion level). Each GPIO input pin is latched at the beginning of a read cycle. These bits can be individually programmed as input (with selectable pull-up resistor) or output (with selectable drive strength). Each MPIO input pin is latched at the beginning of a read cycle.
Other pins when configured as PIO
I/O
Y
IOHPP H
Table 17. SIM Signals
Signal Name RESET RSTOUT Dir I O N Y Y I/O Cell INHP OTP External Reset (active low) Reset Output (active low) Description
26
MMC2080/2075 Technical Data Preliminary
Tables of Signals
Table 18. JTAG/OnCETM Signals
Signal Name TMS TCK TDI TDO TRST DE Dir I I I O I I/O N Y Y Y Y Y Y I/O Cell INHPP INHPP INHPP OTP INHP IOHPPH Description Test Mode Select--Pull-up resistor always enabled Test Clock--Pull-up resistor always enabled Test Data In--Pull-up resistor always enabled Test Data Out TAP Reset (active low) Debug Enable (open drain, active low)
Table 19. Clock and Power
Signal Name EXTAL XTAL CXFC VddCore (5) VssCore(5) VddIO (11) VssIO (11) VddOSC VssOSC VddPLL VssPLL N Y Y Y Y Y Y Y Y Y Y Y I/O Cell AIN AOT AIN Power Power Power Power Power Power Power Power Description Oscillator circuit input--external 76.8 kHz crystal Oscillator circuit output PLL filter capacitor Core power Core ground I/O pad power I/O pad ground Oscillator power Oscillator ground PLL power PLL ground
Table 20. Arbitration Signals
Signal Name BREQ Dir I N Y I/O Cell INHPP Description Arbitration Request (active low)--Request mastership of the internal system bus; pull-up resistor always enabled Arbitration Grant (active low)--Indicates system bus is granted to external master
BGNT
O
Y
OTP
Signal and Connection Descriptions Preliminary
27
General Characteristics
Part 3 Specifications
3.1 General Characteristics
The MMC2080/2075 specifications are preliminary, from design simulations, and may not be fully tested or guaranteed at this early stage of the product life cycle. Finalized specifications will be published upon the completion of full characterization and device qualifications.
3.2 Maximum Ratings
WARNING:
This device contains circuitry protecting against damage due to high static voltage or electrical fields; however, normal precautions should be taken to avoid exceeding maximum voltage ratings. Reliability is enhanced if unused inputs are tied to an appropriate logic voltage level (for example, either Vss or Vdd).
NOTE:
In the calculation of timing requirements, adding a maximum value of one specification to a minimum value of another specification does not yield a reasonable sum. A maximum specification is calculated using a worst-case variation of process parameter values in one direction. The minimum specification is calculated using the worst-case variation for the same parameters in the opposite direction. Therefore, a "maximum" value for a specification will never occur in the same device that has a "minimum" value for another specification; adding a maximum to a minimum represents a condition that can never exist.
Table 21. DC Absolute Maximum Operating Conditions
Characteristics Supply (All) Input Voltage Range Input Clamp Current (V1<0 or V1>QVDDH) Output Clamp Current (V1<0 or V1>QVDDH) Storage Temperature Range Symbol Vdd VI II Min 1.8 Typ 3.0 Max 3.6 V V mA Units
IO
mA
o
C
Remaining specification information to be provided.
28
MMC2080/2075 Technical Data Preliminary
BGA Details
Part 4 Pin-out and Package Information
This section provides information about the available packages for this product. The MMC2080/2075 is available in a 144-pin Ball Grid Array (BGA) package. A 208-pin Pin Grid Array (PGA) is produced for engineering use only. Contact the factory for availability.
4.1 BGA Details
The MMC2080/2075 is offered in the JEDEC-standard, Mold Array Process (MAP), 12 mm x 12 mm BGA with 0.8 mm ball pitch (0.4 mm small solder balls). Refer to Figure 8 for the package drawings and dimensions.
4.1.1
X Y
BGA Package Mechanical Drawings
D
LASER MARK FOR PIN 1 IDENTIFICATION IN THIS AREA
The mechanical drawings for the 144-pin Ball Grid Array package are shown in Figure 8.
DETAIL K M
E
NOTES: 1. DIMENSIONS ARE IN MILLIMETERS. 2. INTERPRET DIMENSIONS AND TOLERANCES PER ASME Y14.5M, 1994. 3. DIMENSION b IS MEASURED AT THE MAXIMUM SOLDER BALL DIAMETER, PARALLEL TO DATUM PLANE Z. 4. DATUM Z (SEATING PLANE) IS DEFINED BY THE SPHERICAL CROWNS OF THE SOLDER BALLS. 5. PARALLELISM MEASUREMENT SHALL EXCLUDE ANY EFFECT OF MARK ON TOP SURFACE OF PACKAGE.
M 0.15
12X
DIM A A1 A2 b D E e
MILLIMETERS MIN MAX 1.25 1.60 0.18 0.34 1.16 REF 0.35 0.45 12.00 BSC 12.00 BSC 0.80 BSC
e
2 1 A B C D E F G H J K L M N
METALIZED MARK FOR PIN 1 IDENTIFICATION IN THIS AREA
13 12 11 10 9
8
5
4
3
12X
e
5 A A2 0.20 Z
A1
Z
4
0.10 Z
3
144X
b VIEW M-M
ROTATED 90 CLOCKWISE
DETAIL K
0.15 Z X Y 0.08 Z
Figure 8. MMC2080/2075 BGA Mechanical Drawings
Pin-out and Package Information Preliminary
29
PGA Details
4.2 PGA Details
The MMC2080/2075 is also offered in a ceramic, 43 mm x 43 mm PGA for engineering use only. Contact the factory for availability. Refer to Figure 9 for the package drawings and dimensions.
4.2.1
PGA Package Mechanical Drawings
The mechanical drawings for the 208-pin Ball Grid PGA package are shown in Figure 9.
F C D A G
SEATING PLANE NOTES: 1. DIMENSIONS ARE IN MILLIMETERS. 2. INTERPRET DIMENSIONS AND TOLERANCES PER ASME Y14.5M, 1994. 3. MINIMUM SPACING BETWEEN CONDUCTORS SHALL BE 0.500. DIM D E F G H K L b e MILLIMETERS MIN MAX 42.70 43.70 42.70 43.70 1.78 3.68 1.14 1.90 0.08 ----2.00 2.54 5.00 0.40 0.50 2.54 BSC
E
L B 0.200 C
16X A B C D E F G H J K L M N P R T U 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1
e
K
4X
H
16X
e
208X
b 0.500 0.250
M M
CA C
M
B
M
Figure 9. MMC2080/2075 PGA Mechanical Drawings
30
MMC2080/2075 Technical Data Preliminary
Ordering Drawings
4.3 Ordering Drawings
Complete mechanical information regarding MMC2080/2075 packaging is available by facsimile through Motorola's MFAXTM system. Call the following number to obtain information by facsimile:
(602) 244-6591
The MFAX automated system requests the following information: * * The receiving facsimile telephone number, including area code or country code The caller's personal identification number (PIN)
NOTE:
For first-time callers, the system provides instructions for setting up a PIN, which requires the entry of a name and telephone number. * The type of information requested: -- Instructions for using the system -- A literature order form -- Specific-part technical information or datasheets -- Other information described by the system messages A total of three documents may be ordered per call. The MMC2080/2075 144-pin BGA package mechanical drawing is referenced as Case 1248A-01 Rev. 0. The MMC2080/2075 208-pin BGA package mechanical drawing is referenced as Case 1297-01 Rev. 0.
Pin-out and Package Information Preliminary
31
Heat Dissipation
Part 5 Design Considerations
5.1 Heat Dissipation
An estimate of the MMC2080/2075 chip junction temperature, TJ, in C can be obtained from the following equation.
T J = T A + ( PD x R JA )
Where: TA = ambient temperature C RJA = package junction-to-ambient thermal resistance C/W PD = power dissipation in package Historically, thermal resistance has been expressed as the sum of a junction-to-case thermal resistance and a case-to-ambient thermal resistance, as follows:
RJA = R JC + RCA
Where: RJA = package junction-to-ambient thermal resistance C/W RJC = package junction-to-case thermal resistance C/W RCA = package case-to-ambient thermal resistance C/W RJC is device related and cannot be influenced by the user. The user controls the thermal environment to change the case-to-ambient thermal resistance, RCA. For example, the user can change the air flow around the device, add a heat sink, change the mounting arrangement on the printed circuit board, or otherwise change the thermal dissipation capability of the area surrounding the device on a printed circuit board. This model is most useful for ceramic packages with heat sinks; ninety percent of the heat flow is dissipated through the case to the heat sink and out to the ambient environment. For ceramic packages, in situations where the heat flow is split between a path to the case and an alternate path through the printed circuit board, analysis of the device's thermal performance may need the additional modeling capability of a system-level thermal simulation tool. The thermal performance of plastic packages is more dependent on the temperature of the printed circuit board to which the package is mounted. Again, if the estimations obtained from RJA do not satisfactorily answer whether the thermal performance is adequate, a system-level model may be appropriate. A complicating factor is the existence of three common ways for determining the junction-to-case thermal resistance in plastic packages: * To minimize temperature variation across the surface, the thermal resistance is measured from the junction to the outside surface of the package (case) closest to the chip mounting area when that surface has a proper heat sink. To define a value approximately equal to a junction-to-board thermal resistance, the thermal resistance is measured from the junction to where the leads are attached to the case. If the temperature of the package case (TT) is determined by a thermocouple, the thermal resistance is computed using the value obtained by the equation (TJ - TT)/PD.
* *
As noted previously, the junction-to-case thermal resistances quoted in this document are determined using the first definition. From a practical standpoint, this value is also suitable for determining the junction
32
MMC2080/2075 Technical Data Preliminary
Electrical Design Considerations
temperature from a case thermocouple reading in forced convection environments. In natural convection, using the junction-to-case thermal resistance to estimate junction temperature from a thermocouple reading on the case of the package will estimate a junction temperature slightly hotter than the actual temperature. Hence, the new thermal metric, thermal characterization parameter or JT, has been defined to be (TJ - TT)/ PD. This value gives a better estimate of the junction temperature in natural convection when using the surface temperature of the package. Remember that surface temperature readings of packages are subject to significant errors caused by inadequate attachment of the sensor to the surface and to errors caused by heat loss to the sensor. The recommended technique is to attach a 40-gauge thermocouple wire and bead to the top center of the package with thermally conductive epoxy.
NOTE:
Section 3, "Specifications," on page 28 of this document contains the package thermal values for this chip.
5.2 Electrical Design Considerations
WARNING:
This device contains protective circuitry to guard against damage due to high static voltage or electrical fields. However, normal precautions are advised to avoid application of any voltages higher than maximum rated voltages to this high-impedance circuit. Reliability of operation is enhanced if unused inputs are tied to an appropriate logic voltage level (for example, either Vss or VDD). Use the following list of recommendations to assure correct operation: * * * * * Provide a low-impedance path from the board power supply to each Vdd pin on the MMC2080/ 2075 and from the board ground to each Vss pin. Use at least four 0.1 F bypass capacitors positioned as close as possible to the four sides of the package to connect the Vdd power source to Vss. Ensure that capacitor leads and associated printed circuit traces that connect to the chip Vdd and Vss pins are less than 0.5 inch per capacitor lead. Use at least a four-layer printed circuit board (PCB) with two inner layers for Vdd and Vss. Consider all device loads as well as parasitic capacitance due to PCB traces when calculating capacitance. This is especially critical in systems with higher capacitive loads that could create higher transient currents in the Vdd and Vss circuits. All inputs must be terminated (that is, not allowed to float) using CMOS levels.
*
Take special care to minimize noise levels on the PLL supply pins (both Vdd and Vss).
Design Considerations Preliminary
33
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